Method for pre-verifying software/hardware design of communication system

ABSTRACT

A pre-verifying method for software/hardware design of a communication system includes simulating a process of sending a data frame from a transmitter to a receiver with a transceiver algorithm meeting a preset specification for obtaining simulation parameters. A transmitter hardware platform sends the data frame via an antenna. A receiver hardware platform receives an echo signal of the data frame and compares each parameter of the echo signal with the simulation parameters. The comparison result of various parameters of the echo signal and the simulation parameters is verified to be in a desired range or not. When the comparison result is not in the desired range, the transceiver algorithm is adjusted. When the comparison result is in the desired range, the transceiver algorithm is converted to a hardware program language format to be written in a programmable module to perform the action of the transmitter and the receiver.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/271,414,filed on Nov. 9, 2005, now pending. The entirety of each of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a wireless communication equipment andpre-verifying method for software/hardware designing thereof. Moreparticularly, the present invention relates to a MIMO-CDMA wirelesscommunication equipment, and pre-verifying method for software/hardwaredesign of communication system having verification of comparing thesystem simulation with the hardware realization.

2. Description of Related Art

With the rapid development of the wireless communication techniques, thewireless broadband and high speed data transmission has been a primaryrequirement of the next generation mobile communication system. Forthese objects, the space resource will be employed (i.e. multipleantennas are used at the transmitting end and the receiving end toimprove the system performance). Therefore, it is very important todiscuss the related multi-path, multi-input, multi-output channel anddevelop the Space-time Processing algorithm. On the other hand,multi-wave orthogonal frequency division multiplexing (OFDM) modulationtransmission is an extremely preferable technique for resisting thefrequency selective fading resulted form outdoor multiple path effect.But since the OFDM technique means composing all subcarrier datatransmissions, the peak-to-average power ratio (PAPR) and the dynamicrange are too large, causing the problems of quantization distortion ofanalog/digital converter, digital/analog converter and radio frequencypower amplifier, which influence the performance.

SUMMARY OF THE INVENTION

In view of the above, the present invention is directed to a MIMO-CDMAwireless communication equipment, which has a higher range of dynamicflexible adjustment based on the change of the environment, and provideshigher power efficiency and low transmitter complexity.

The present invention is further directed to a pre-verifying method forsoftware/hardware design of communication system, to verify thecorrectness of the algorithm developed for communication system rapidly.

The present invention provides a MIMO-CDMA wireless communicationequipment including a transmitter and a receiver. The transmitterincludes an encoder for receiving and encoding a plurality oftransmission data, and then sending them to a QPSK unit. The QPSK unitconducts QPSK modulating to an output of the encoder and sends it to aspace-time block coding (STBC) unit to conduct space-time coding.Furthermore, a plurality of data frame generating modules generate adata frame respectively based on the output of the STBC unit, aplurality of preamble codes generated by a preamble code spreading unit,a pilot code and a cyclic prefix (CP). The data frames are sent to thereceiver via a transmitting antenna respectively.

From another point of view, the present invention further provides aMIMO-CDMA wireless communication equipment including a transmitter and areceiver as the same. The transmitter also includes an encoder forreceiving and encoding a plurality of transmission data, and thensending the data to a QPSK unit, except that the QPSK unit conducts QPSKmodulating to an output of the encoder and sends it to a spacemultiplexer to conduct space coding. Then, a plurality of data framegenerating modules generate a data frame respectively based on theoutput of the space multiplexer, a plurality of preamble codes generatedby a preamble code spreading unit, a pilot code and a cyclic prefix. Thedata frames are also sent to the receiver via a transmitting antennarespectively.

In the embodiment of the present invention, the receiver includes aplurality of receiving antennas for receiving the data frames from eachcorresponding transmitting antenna respectively, and sending themcorrespondingly to a plurality of radio frequency units respectively, toconduct frequency reducing to the received data frames. Furthermore, aplurality of estimation modules are coupled correspondingly to the radiofrequency units respectively, for estimating a time parameter, afrequency parameter and a channel parameter of the frequency reduceddata frame, and removing the cyclic prefix. And a decision demodulatingmodule receives the output of each estimation module to conduct dataspreading to the data frame passed through the estimation module, so asto conduct space-time block decoding or interference eliminating, andsend the data frame to a decoder to revert the original transmissiondata.

From another point of view, the present invention provides apre-verifying method for software/hardware design of communicationsystem adapted to verify the communication system having a transmitterand a receiver. The present invention includes simulating the process ofsending a data frame from the transmitter to the receiver with atransceiver algorithm meeting a preset specification, so as to obtainplurality of simulation parameters; and then, planning the transmitterhardware platform to send the data frame via an antenna. The transmitterhardware platform has programs meeting the above preset specification.Furthermore, the receiver hardware platform is planned to receive theecho signal of the data frame and compare each parameter of this echosignal to the above simulation parameters. At this time, verifying theresult of comparing various parameters of the above echo signal and thesimulation parameters is within a desired range or not. When the resultof comparing various parameters of the above echo signal and thesimulation parameters is not in a desired range, the above transceiveralgorithm will be adjusted. Otherwise, if the result of comparingvarious parameters of the above echo signal and the simulationparameters is in a desired range, the transceiver algorithm will beconverted to a hardware program language format to be written in aprogrammable module to perform the action of the transmitter and thereceiver.

Since the wireless communication equipment provided in the presentinvention employs the MIMO-CDMA technique, and it is a single wavetime-space domain spreading technique, the signal dynamic range is notlarge, and the occupancy to digital/analog converter or digital/analogconverter bit number is not large, therefore, a high dynamic flexibleadjustment range can be obtained according to the change of theenvironment. Furthermore, since the single wave is not sensitive to thenon-linearity of the radio frequency power amplifier, the presentinvention has the advantage of higher power efficiency and lowtransmitter complexity.

Further, the pre-verifying method provided in the present invention canverify the application of the algorithm developed for communicationsystem correctly and rapidly, due to the practical comparison betweenthe results from the system simulation and hardware operation.

In order to the make the aforementioned and other features andadvantages of the present invention apparent, the preferred embodimentsin accompany with drawings is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a transmitter havingmulti-output according to a preferred embodiment of the presentinvention.

FIG. 2 is a functional block diagram of a data spreader according to apreferred embodiment of the present invention.

FIG. 3 is a schematic view of a data frame format according to apreferred embodiment of the present invention.

FIG. 4 is a functional block diagram of a receiver having multi-inputaccording to a preferred embodiment of the present invention.

FIG. 5 is a circuit block diagram of an estimation module according to apreferred embodiment of the present invention.

FIG. 6 is a circuit block diagram of a decision demodulating moduleaccording to a preferred embodiment of the present invention.

FIG. 7 shows a flow chart of a pre-verifying method forsoftware/hardware design of communication system according to apreferred embodiment of the present invention.

FIG. 8 shows a verifying system for software/hardware design ofcommunication system meeting the verifying method of FIG. 7.

DESCRIPTION OF EMBODIMENTS

FIG. 1 is a functional block diagram of a transmitter havingmulti-output according to a preferred embodiment of the presentinvention. The transmitter is adapted to a MIMO-CDMA wirelesscommunication equipment. Referring to FIG. 1, the transmitter 100 of thepresent invention has an encoder 102 with its output coupled to aquadrature phase-shift keying (QPSK) unit 104. The output of the QPSKunit 104 is coupled to a space-time block coding (STBC) unit 106. In thetransmitter 100, a plurality of data frame generating modules arefurther provided, for example, 120, 140, for receiving the outputs ofthe STBC unit 106 and a preamble code spreading unit 108.

Still referring to FIG. 1, the encoder 102 receives a plurality oftransmission data d1, d2, . . . , dn, and encodes the data. Next, theQPSK unit 104 will conduct QPSK modulating to the output of the encoder102 to generate a plurality of QPSK symbol, and then spread the QPSKsymbol with Walsh-Hadamard Orthogonal spreading, thereby obtaining aspread code gain to be output to the STBC unit 106. After the STBC unit106 receives the output of the QPSK unit 104, it will conduct space-timeblock coding to the output, which can be represented by the mathematicalexpression below:

$\left\lbrack {d_{2}\mspace{20mu} d_{1}} \right\rbrack->\begin{bmatrix}{- d_{2}^{*}} & d_{1} \\d_{1}^{*} & d_{2}\end{bmatrix}$

where, d1 and d2 are all transmission data. Then, the STBC unit 106 willsend the output to the data frame generating module 120 and 140respectively.

In another alternative embodiments, the STBC unit 106 can be replaced bya space multiplexer. The space multiplexer can conduct space coding tothe output of the QPSK unit 104, which can be represented by themathematical expression below.

$\left\lbrack {d_{2}\mspace{20mu} d_{1}} \right\rbrack->\begin{bmatrix}d_{1} \\d_{2}\end{bmatrix}$

Still referring to FIG. 1, the data frame generating module 120 can beprovided with a data spreader 122 for receiving the output of the STBCunit 106 or the space multiplexer. Furthermore, the output of the dataspreader 122 is coupled to one output end of a multiplexer 124, whilethe other input end of the multiplexer 124 is the output of receivingthe preamble code spreading unit 108. Therefore, the multiplexer 124 cansend the output of the preamble code spreading unit 108 or the dataspreader 124 to a digital/analog converter 126 selectively. Thedigital/analog converter 126 is coupled to a transmitting antenna 130 bya radio frequency unit 128.

Similarly, the data frame generating module 140 also includes a dataspreader 142, a multiplexer 144, a digital/analog converter 146 and aradio frequency unit 148. The output of the radio frequency unit 148 iscoupled to the transmitting antenna 150. The connection of the abovemeans is the same as that of the data frame generating module 120.Definitely, the function and operation of each means of the data framegenerating module 140 are similar to that of the data frame generatingmodule 120. Therefore, the data frame generating module 120 will betaken as an example for illustration, and those skilled in the art willunderstand that the data frame generating module 140 can also be used.

For the present embodiment, when the output of the STBC unit 106 is sentto the data frame generating module 120, the data spreader 142 willspread the output of the STBC unit 106. In order to resist the influenceof multi-path of the wireless channel, a pilot code is further addedafter a cyclic prefix (CP) similar to multiple wave orthogonal frequencydivision multiplexing (OFDM) is added to the output of the STBC unit106, so as to create a payload data to the multiplexer 124.

FIG. 2 is a functional block diagram of a data spreader according to apreferred embodiment of the present invention. Referring to FIG. 2, inthe present invention, the aforementioned data spreader 122 can include,for example, a data spreading unit 211, a cyclic prefix generating unit213, a pilot codes generating unit 215 and an adder 217.

The data spreading unit 211 is used to spread the output of the STBCunit 106, then output it to the cyclic prefix generating unit 213. Thecyclic prefix generating unit 213 will add a cyclic prefix to the outputof the data spreading unit 211, then sends it to the adder 217.

Moreover, the pilot code generating unit 215 is used to generate a pilotcode, and the output thereof will also coupled to the adder 217.Therefore, the adder 217 will add the output of the cyclic prefixgenerating unit 213 and the output of the pilot code generating unit 215to generate a payload data.

Referring back to FIG. 1, after the multiplexer 124 receives, forexample, the payload data output from the adder 217 of FIG. 2, it willgenerate a data frame in accompany with the preamble code spreading unit108. The preamble codes are used from tracing the offset of thesubsequent phase shift.

FIG. 3 is a schematic view of a data frame format according to apreferred embodiment of the present invention. Referring to FIGS. 1 and3, in the present invention, the multiplexer 124 will firstly select thepreamble codes generated by the preamble code spreading unit 108 as theoutput. As shown in FIG. 3, the preamble codes generated by the preamblecode spreading unit 108 can be used for frame detecting, timeestimation, frequency estimation, channel estimation and the like. Inthe present invention, the multiplexer 124 is required to output 8preamble codes, and then switch to the data spreader 122 to outputpayload data. It can be seen from FIG. 3, in the payload data, a pilotcode will also be added besides the received transmission data for thesubsequent phase estimation and time tracing.

Still referring to FIG. 1, after the multiplexer 124 outputs, forexample, the data frame shown in FIG. 3 to the digital/analog converter126, the digital/analog converter 126 will convert the data frame toanalog signal, and send it to the radio frequency unit 128. And afterthe radio frequency unit 128 increases the frequency of the output ofthe digital/analog converter 126 to the radio frequency, the output willbe sent by the transmitting antenna 130.

Although in FIG. 1, the number of the data frame modules and thetransmitting antennas is 2, it is known to those skilled in the art thatthe embodiment of FIG. 1 is only for illustration, and will not limitthe present invention. It is similar to the receiver described below.

FIG. 4 is a functional block diagram of a receiver having multi-inputaccording to a preferred embodiment of the present invention, which isalso adapted to the MIMO-CDMA wireless communication equipment.Referring to FIG. 4, the receiver of the present invention includes aplurality of receiving antennas correspondingly coupled to a radiofrequency unit respectively. For example, in the receiver 400, thereceiving antennas 402, 404 are coupled to the radio frequency units406, 408 respectively. And each of the radio frequency units is coupledto an estimation module, for example, the radio frequency units 406, 408coupled to the estimation modules 410, 412 respectively. The outputs ofall estimation modules will be coupled to a decision demodulating module414, and the output of the decision demodulating module 414 is sent to adecoder 416.

Still referring to FIG. 4, the receiving antennas 402, 404 are used forreceiving, for example, frame data sent by the transmitter 100 of FIG.1, and each of the receiving antennas corresponds to a transmittingantenna. Taking the receiving antenna 402 as an example, the antennawill reducing the frame data to the base frequency signal through theradio frequency unit 406 after receiving the frame data, and then sendit to the estimation module 410 to be processed.

FIG. 5 is a circuit block diagram of an estimation module according to apreferred embodiment of the present invention. Referring to FIG. 5, theestimation units 410, 412 in FIG. 4 can include, as shown in FIG. 5, aanalog/digital converter 501, a time/frequency synchronization unit 503,a channel estimation unit 505, a cyclic prefix removing unit 507, and aphase estimation unit 509.

Referring to FIGS. 4 and 5, for example, when the output of the radiofrequency unit 406 is sent to the estimation module 410, theanalog/digital converter 501 in the estimation module 410 will convertthe output to digital signal at first, and then send it to thetime/frequency synchronization unit 503, the channel estimation unit 505and the cyclic prefix removing unit 507. The time/frequencysynchronization unit 503 will estimate the time and frequency parametersof the data frame received by the receiving antenna 402 based on theabove preamble codes, and then send the output to the cyclic prefixremoving unit 507 to remove the cyclic prefix. Furthermore, the channelestimation unit 505 estimates the channel parameter of the data framebased on the preamble codes, and the output A1 thereof is sent to thedecision demodulation unit 414.

After the cyclic prefix removing unit 507 removes the cyclic prefix ofthe data frame, it also sends the output A2 thereof to the decisiondemodulating module 414. Moreover, the phase estimation unit 509 willestimate the phase of the output of the cyclic prefix removing unit 507based on the above pilot codes, and the output A3 thereof is alsocoupled to the decision demodulation unit 414.

Although a estimation module 410 is taken as an example in the abovedescription, it is known to those skilled in the art that the estimationmodule 412 can also be used.

FIG. 6 is a circuit block diagram of a decision demodulating moduleaccording to a preferred embodiment of the present invention, which isadapted to the decision demodulating module 414 of FIG. 4. Referring toFIGS. 4 and 6, the decision demodulating module 414 can include adecision unit 601 and a QPSK demodulation unit 603. When the outputs A1,A2 and A3 of the estimation module are sent to the decision demodulatingmodule 414, the decision unit 601 will spread and compensate the outputsA1, A2 and A3 of the estimation module, and conduct space-time blockdecoding. Contrarily, in other embodiments, if the STBC unit 106 in thetransmitter 100 of FIG. 1 is replaced by the space decoder, the decisionunit 601 conducts interference elimination instead of space-time blockdecoding.

Then, the output of the decision unit 601 will be sent to the QPSKdemodulation unit 603, to convert the output of the decision unit 601back to the QPSK symbol. Then, the output of the QPSK demodulation unit603 will be sent to the decoder 416 to revert the original transmissiondata d1, d2, . . . , dn.

In order to verify the correctness of the communication systemconsisting of the transmitter 100 and the receiver 400 of the FIGS. 1and 4, the present invention further provides a pre-verifying method forsoftware/hardware design of communication system, as shown in FIG. 7.Referring to FIG. 7, when a communication system having a transmitterand a receiver is to be designed, a transceiver algorithm is firstlydesigned according to a preset specification. In the present embodiment,the developers can design the transceiver algorithm with MATLABsoftware.

When the design of the transceiver algorithm is completed, a possibleprocess of sending a data frame from the transmitter to the receiver canbe simulated with this transceiver algorithm, and a plurality ofsimulation parameters can be obtained, as shown in step S701. In thepresent embodiment, step S701 mainly simulates the following states.

1. Simulating the state of the transmitter: an encoded spreading signalhaving QPSK modulation is generated with MATLAB Comm. Tool Box, andafter the simulated base frequency signal is sampled and pulse shaped,the transmission signal of band-pass radio frequency is simulated underthe equivalent base frequency I/Q model.

2. Simulating the channel environment: in order to simulate the possiblesituation in real environment, the transmission signal is added withchannel effect including Additive White Gaussian Noise channel (AWGNChannel) effect and Rayleigh Fading channel effect. Moreover, in orderto simulate the real transceiver, the effect of frequency offset betweenthe oscillators of the transmitter and the receiver and the simulationof the signal propagation delay between the transmitter and the receiverare also added in the present invention.

3. Simulating the state of the receiver: simulate the echo signalinfluenced by the channel, and process the synchronization estimationand compensation with the de-spread technique of the above preamblecodes and the pilot code, thereby decoding to revert original signal.

After the step S701 is completed, the present invention proceeds to stepS703, that is, planning the transmitter hardware platform, to actuallysend out the data frame via an antenna. Then, as described in step S705,plan the receiver hardware platform to receive the echo signal of thedata frame sent by the transmitter, and compare each of the parametersof the echo signal and the above simulation parameters, so as to verifywhether the result of comparing each of the parameters of the echosignal and the above simulation parameters is within a desired range ornot, as described in step S709.

When the result of comparing each of the parameters of the echo signaland the above simulation parameters does not fall within the desiredrange (“NO” indicated in step S709), the content of the abovetransceiver algorithm needs to be adjusted such that it can meet thedesired better effect, as described in step S711.

Contrarily, When the result of comparing each of the parameters of theecho signal and the above simulation parameters fall in the desiredrange (“YES” indicated in step S709), the transceiver algorithm isconverted to a hardware language, e.g. Verilog or VHDL and the like asdescribed in step S713, such that it can be written into a programmablemodule to perform the action of the transmitter and the receiver asdescribed in step S715.

FIG. 8 shows a verifying system for software/hardware design ofcommunication system meeting the verifying method of FIG. 7. Referringto FIGS. 7 and 8, in FIG. 8, a system simulation part 810 and a hardwarepart 820 are included. The system simulation part 810 described in stepS701 includes a transmitter algorithm 812 for simulating transmitterstate, a channel model 814 for simulating real channel state, and areceiver algorithm 816 for simulating receiver state. And the simulationmanner of these systems has been described above, and will not bedescribed herein again.

In the hardware part 820, a transmitter hardware platform 830 and areceiver hardware platform 850 are included. The transmitter hardwareplatform 830 includes a charge coupled device (CCD) camera 832 forcapturing image information. Furthermore, a read only memory (ROM) 834can also be included in the transmitter hardware platform 830, to storethe transmission signal meeting the preset specification.

After the transceiver hardware platform is activated, the transmitterhardware platform 830 will send the transmission signal stored in theROM 834 in form of data frame to the receiver hardware platform 850 viaa real channel environment.

After the receiver hardware platform 850 receives the echo signal of thedata frame, a logic analyzer (LA) 852 will capture the digital signal,and various parameters of the digital signal are then analyzed under theMATLAB environment. Then these parameters are compared with the variousparameters generated by the system simulation part 810 to be thereference of the adjustment by the developers.

When the result of comparing the various parameters of the echo signaland the simulation parameters generated by the system simulation part810 is within a desired range, the transmitter algorithm 812 and thereceiver algorithm 816 in the system simulation part 810 are convertedto hardware language form, and are written into a field programmablegate array (FPGA) 838 of the transmitter hardware platform 830 and aFPGA 858 of the receiver hardware platform 850 respectively, therebyreplacing the function of the ROM 834 and logic analyzer 852 by theFPGAs 838, 858.

In view of the above, the present invention can capture real-timedynamic image with a CCD camera 832, and then send the image informationin form of data frame through a USB 836 via a real channel environmentto the receiver to be processed. The image information is displayed onthe display 856 through a USB 854 to realize a verifying scheme usingcomparison between the software and hardware, such that thecommunication system developed by the developers can be verified rapidlyand correctly.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A pre-verifying method for software/hardware design of acommunication system having a transmitter and a receiver, thepre-verifying method comprising: simulating a process of sending a dataframe from the transmitter to the receiver with a transceiver algorithmmeeting a preset specification, and obtaining a plurality of simulationparameters; planning a transmitter hardware platform to send out a dataframe via an antenna, the transmitter hardware platform having atransmission signal meeting the preset specification; planning areceiver hardware platform to receive an echo signal of the data frame,and comparing various parameters of the echo signal with the simulationparameters; verifying whether the result of comparing the variousparameters of the echo signal and the simulation parameters is within adesired range; adjusting the transceiver algorithm if the result ofcomparing the various parameters of the echo signal and the simulationparameters is not within the desired range; and converting thetransceiver algorithm to a hardware program language format to bewritten into a programmable module to perform an action of thetransmitter and the receiver if the result of comparing the variousparameters of the echo signal and the simulation parameters is in thedesired range.
 2. The pre-verifying method for software/hardware designof the communication system as claimed in claim 1, wherein thesimulating step using the receiver algorithm comprises: simulating thestate of the transmitter, including generating an encoded spreadingsignal having QPSK modulation by the MATLAB program language, andsampling and pulse shaping the encoded spreading signal; simulating thechannel environment, to simulate the possible situation of the dataframe transmitted by the transmitter in real environment, and adding aplurality of channel effects to the data frame, the channel effectsincluding Additive White Gaussian Noise (AWGN) channel effect andReyleigh Fading channel effect; and simulating the state of thereceiver, to simulate the situation of the receiver receiving the echosignal of the data frame.
 3. The pre-verifying method forsoftware/hardware design of the communication system as claimed in claim2, wherein the step of simulating the channel environment furthercomprises simulating the oscillating frequency offset effect between thetransmitter and the receiver, and simulating the signal propagationdelay between the transmitter and the receiver.
 4. The pre-verifyingmethod for software/hardware design of the communication system asclaimed in claim 1, wherein the step of planning the transmitterhardware platform comprises: sending the data frame to the receiver viaa transmitter radio frequency unit and the antenna, based on thetransmission signal stored in a read-only memory (ROM).
 5. Thepre-verifying method for software/hardware design of the communicationsystem as claimed in claim 1, wherein the step of planning the receiverhardware platform comprises: analyzing the echo signal of the data framewith a logic analyzer and MATLAB, to compare it with the simulationparameters; and displaying the image information on a display through asecond universal serial bus (USB).
 6. The pre-verifying mryhof forsoftware/hardware design of the communication system as claimed in claim1, wherein the programmable module is a field programmable gate array(FPGA).